The present invention relates to semiconductor integrated circuit devices which are applicable to dynamic random access memories (DRAM) for which the word line voltage is raised, and more particularly, relates to semiconductor integrated circuit devices that can be compatible with high-speed transmission of data and an improvement of reliability of a transfer transistor by changing a step-up level in a gate of the transfer transistor before and after activation of a sense amplifier.
One known type of semiconductor integrated circuit device is provided with a data retention node N.sub.D, a data line DL that is precharged to a required voltage, a sense amplifier connected to this data line DL, a data retention node N.sub.D having a source and a drain, an NMOS transistor (hereinafter termed a transfer transistor) connected to the data line DL, and a voltage raise circuit connected to a gate of this NMOS transistor. In this semiconductor integrated circuit device, the data transfer between the node N.sub.D and the data line DL is performed by the following procedure.
First, in order to output the data of the node N.sub.D to the data line DL, the gate of the transistor that is 0 V at the start of the operating period is made a high potential by the voltage raise circuit and when this occurs, the transistor turns on and there is an electrical connection between the node N.sub.D and the data line DL. By this, the data of the node N.sub.D changes the potential of the data line DL from the precharge potential. After this, the sense amplifier is activated and the level change of the data line is amplified, and the data line is then either high or low. Data is output from the node N.sub.D to the data line DL when there is this status.
After this, data is input to the node N.sub.D via the data line DL. If the gate of the transistor is held as it is at this potential, then the node N.sub.D and the data line DL are electrically connected by a transfer transistor and so the data of node N.sub.D becomes the same as that of the data line DL. If the data of the data line DL is inverted, then data that is the same as the data that was output from the node N.sub.D to the data line DL with the prior transfer, is transferred from the data line DL to the node N.sub.D, and if the data of the data line is inverted by an input circuit, then the reverse data is transferred to the node N.sub.D. When the transfer operation finally ends, the gate voltage is made 0 V, and the transfer transistor turns off, and the node N.sub.D and the data line DL are electrically interrupted, and the data line DL is charged to a predetermined voltage and preparations are made for the next data transfer.
A typical type of transfer transistor as described above is a DRAM memory cell transistor. The following is a description of an example of this. FIG. 1 is a view of a conventional semiconductor integrated circuit device. This semiconductor integrated circuit device is a DRAM, and for the purpose of simplicity of description, has only a memory cell with two lines and one column. The memory cell comprises one transistor and one capacitor, and the respective memory cells are termed MC0, MC1, and the transistor and the capacitor that configure each memory cell are termed TM0, CM0, TM1, CM1. Moreover, the data retention node N.sub.D is formed by the nodes N.sub.D0 and N.sub.D1 provided to the cells M.sub.C0 and M.sub.C1. The memory cell transistor TM0 has the gate connected to the word line WL0, and the source and the drain connected between the bit line BL0 and the capacitor CM0. In the same manner, the memory cell transistor TM1 has the gate connected to the word line WL1, and the source and the drain connected between the bit line BBL0 and the capacitor CM1. Moreover, the initial character "B" of the bit line BBL0 means an "inversion" and the bit line BBL0 transfers data which are inverted with respect to the data that are transferred by the bit line BL0. The bit lines BL0 and BBL0 are connected to the sense amplifier SA, and the word lines WL0, WL1 are connected to the output node WD of the word line voltage raise circuit WLDV via the decoder DC. The word line voltage raise circuit WLDV has a transistor T10 that has either the source or the drain connected to a positive voltage V.sub.cc, and the other connected to the output node of the word line voltage raise circuit WLDV, and a transistor T20 that has either the source or the drain grounded, and the other connected to the output node of the word line voltage raise circuit WLDV and inputs the reset signals .phi..sub.R to the gate. The active signal .phi..sub.A are transmitted to the inverter INV1 via an inverter INV2, and the output of the inverter INV1 is supplied to one electrode .phi..sub.A * of a voltage raise capacitor CB1 via the inverter INV2. The other electrode of the voltage raise capacitor CB1 is connected to the output node of the word line voltage raise circuit WLDV.
The following is a description of the operation for the transfer of the data of the memory cell MC0 of the DRAM shown in FIG. 1, to the bit line via the transfer transistor TM0. Here, it is assumed that low data is stored in the memory cell MC0, and that bit lines BL0, BBL0 are precharged to the level of 1/2 of the operating voltage V.sub.cc. To broadly describe the flow operation, the word line WL0 connected to the memory cell MC0 which is to be activated is pulled up from the ground level to above the level of the operating voltage V.sub.cc. When this occurs, the memory cell transistor TM0 conducts and the charge that was stored in the capacitor CM0 flows to the bit line BL0, and the potential of the bit line BL0 drops slightly. When this slight difference in the potential is amplified by the sense amplifier SA, the result is that the bit line BL0 becomes the ground level and the cell data is read.
The start of the read operation creates a potential of greater than the V.sub.cc level by the word line voltage raise circuit WLDV, and the output WD of the word line voltage raise circuit WLDV is transmitted to the object word line WL0 for which the address A has been received from the decoder DC. By making the reset signal .phi..sub.R low and making the active signal .phi..sub.A the V.sub.cc level, the transistor T10 turns on and T20 turns off and the output WD of the word line voltage raise circuit WLDV becomes equal to the level of V.sub.cc -V.sub.t (refer to the period t1 of FIG. 2). Here, V.sub.t is the threshold value of the transistor T10. The active signals .phi..sub.A are transmitted to one electrode of the voltage raise capacitor CB1 via the delay circuit DLY, the inverter INV1 and the INV2, and .phi..sub.A changes to high signals that have a delay. When this occurs, the output WD of the word line voltage raise circuit WLDV rises from the recharged level to the high potential at the period t2 shown in FIG. 2, because of the coupling of the capacitor CB1. In parallel with this operation, the decoder DC receives the address A and the word line WL0 is selected, and the output WD of the word line voltage raise circuit WLDV is transmitted to the word line, and the word line WL0 becomes the voltage raised level V.sub.b (refer to period t2 of FIG. 2).
When the level of the word line WL0 exceeds the threshold value of the memory cell transistor TM0, the transistor TM0 turns on and the data that was stored in the capacitor CM0 flows to the bit line BL0, and the potential of the bit line BL0 makes the sense amplifier activation signals .phi..sub.SA high and activates them, and the level change of the bit line BL0 is amplified, and becomes the ground level (with BBL0 become the V.sub.cc level). In this status, the cell data is read to the bit line (refer to period t3 of FIG. 2).
The gate (word line WL0) of the cell transistor is held at the high potential and so the potential of the bit line BL0 is written to the cell capacitor CM0 via the cell transistor TMO. If the data of the bit line BL0 is not inverted, then low data is written to the cell capacitor CM0, and if the data of the bit line BL0 is inverted, then high data is written to the cell capacitor CM0.
In the reset Operation, when the active signal .phi..sub.A becomes the ground level, the transistor T10 turns off. Also, that for which the active signal .phi..sub.A is low is received and is delayed and .phi..sub.A * becomes low, and because of the coupling of the capacitor CB1, the level of the word line WL0 and the output WD drops to the vicinity of V.sub.cc. At the same time, when the reset signals .phi..sub.R becomes high, when levels of the word line WL0 and the output node WD become the ground level, and the memory cell transistor TM0 turns off and the bit line BL0 and the cell capacitor CM0 are both in the status where they are electrically interrupted (refer to the period t4 of FIG. 2).
The description here assumes that the transfer transistor is an NMOS transistor but the same can be said when it is a PMOS transistor. However, the situation for a PMOS transistor is self evident from the description for an NMOS transistor and so the description of this situation is omitted here. For the same reason, the following description will be for the case of an NMOS transistor only, and is not meant to imply that the present invention is applicable only to transfer transistors that use NMOS transistors.
A transfer transistor must transfer data quickly to a data line that has been precharged. Because of this, the voltage rise potential that is applied to the gate can be as high a voltage as possible. However, this level must be controlled to the degree that there is no destruction of the gate oxide film.
FIG. 1 shows a DRAM for the times when a high voltage is applied to the gate oxide film of a transfer transistor. When the word line WL0 becomes the raised voltage level V.sub.b, the cell data is output to the bit line BL0 (refer to period t2 of FIG. 2). At this time, the gate-source voltage V.sub.gs of the cell transistor TM0 becomes EQU V.sub.gs =V.sub.b -V.sub.cc /2
The potential that is applied to a transfer transistor by the precharge voltage of the bit line even if the gate has had its voltage raised to a high potential is lessened. Following this, when the sense amplifier is activated and the bit line level change is amplified (refer to period t3 of FIG. 2), and in the worst case for when there is the output of low data EQU V.sub.gs =V.sub.b -0
and instead of the voltage raised level of the transfer transistor staying at the voltage raised level, a maximum field is applied to the gate oxide film for this period.
On the other hand, at the period t2 of FIG. 1, it is desirable that the word line voltage raised level be made to as high a potential as is possible, the conductance of the transfer transistor is raised, and the cell data output to the bit line at high speed. On the other hand, at the period t3 of FIG. 1, the raised level of the word line has to be low enough so as not to destroy the gate oxide film. In a conventional semiconductor integrated circuit device, after the sense amplifier has been activated in this manner, there is a high potential difference and so the voltage raise level has to be suppressed. More specifically, there is the danger of destruction of the gate oxide film, and it is not possible to sufficiently raise the transfer efficiency.